1. Field of the Invention
This invention relates to a semiconductor memory device capable of storing 2-level or more data in, for example, a single memory.
2. Description of the Related Art
For example, in a NAND flash memory, each of a plurality of memory cells arranged in the row direction is connected via a bit line to the corresponding latch circuit. Each latch circuit holds data in writing or reading data. The plurality of cells arranged in the row direction are written into or read from simultaneously.
Furthermore, to store large volumes of data, a level memory capable of storing 2 bits or more in a single memory has been developed. Moreover, with the miniaturization of elements, the effect of capacity coupling between the floating gates of a plurality of adjacent cells has become a problem. Specifically, when data is written into a memory cell, the threshold voltage of a memory cell adjacent to the memory cell and previously written into rises due to capacity coupling.
For this reason, the following method has been proposed: for example, when data is read from a first memory cell, the threshold voltage of a second memory cell adjacent to the first memory cell and written into later than the first memory cell is detected, and a correction value corresponding to the detected threshold voltage is added to a read-out voltage in reading data from the first memory cell, thereby reading the data from the first memory cell (e.g., Jpn. Pat. Appln. KOKAI Publication No. 2004-326866).
However, the capacitance between the floating gates of adjacent cells varies very widely from chip to chip or from one word line to another. For this reason, it has been difficult to determine an appropriate correction value. Therefore, a semiconductor memory device capable of setting an appropriate correction value according to the capacitance between the floating gates of adjacent cells has been desired.